I have been reading Behzad Rahzavi's Analog Design book to prepare for interviews and have come across a discussion on calculating poles that confuses me.
In the following example 6.15 the book instructs us to create the following small signal model in Fig 6.12 (b) for the common source topology and to calculate the poles by looking at every node and to:
simply multiply the total equivalent capacitance by the total incremental (small-signal) resistance (both from the node of interest to ground).
However, I think the book is not clear in specifying what to consider as ac ground for this kind of analysis. I understand \$V_{DD}\$ can be considered as ac ground, and that \$R_D\$ can then be seen as the resistance seen from node Y to ground. However, to consider \$R_S\$ the path from node x to the ground seems inconsistent to me, as \$V_{in}\$ in between and normally not ignored in small signal analysis.Other nodes seem to be considered as ground as well with ambiguity. The impedance seen from the source stops at the gm and gm of the transistor and ignores the impedance seen after the drain, stopping at \$V_{out}\$.
I also have doubts on how \$C_{GS}\$ is defined here, as \$V_1\$ is the voltage in between the gate and the source, shouldn't \$C_{GS}\$ be connected to \$V_1\$ in this case and also \$C_{GD}\$? If I vary the input with a small perturbation I should see a small change in x which should look into \$C_{GS}\$ to cause a small signal change in \$V_1\$. So I'm a bit unsure as to why \$C_{GD}\$ and \$C_{GS}\$ are grounded separately from \$V_1\$.